Forum Discussion
2 Replies
- Altera_Forum
Honored Contributor
ModelSim simulates Verilog or VHDL but does not simulate Graphic Design Files (.gdf). In Quartus, "File --> Create/Update --> Create HDL Design File for Current File" might work on a .gdf; I've used that command only on .bdf files.
- Altera_Forum
Honored Contributor
Hi,Brad
thanks very much,I'll simulate in your method