Forum Discussion
Altera_Forum
Honored Contributor
8 years agoI checked the design, screening all the Analysis and Synthesis settings..
Is .sdo the file containing the delay right? So I thought but no matter how many LCELL I introduce, from simulation in ModelSim I always get the same glitch in output (not delayed) as you can see from attached screenshot. I am compiling and simulating the .vo file within ModelSIm, is that correct, does it link automatically to the .sdo? I am trying to simulate the delay introduced by LCELL chains in an already existing project, when I get a full understanding then I will be happy to consider more reliable solution, I guess with .sdc! Thanks a lot for attention!