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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to set_output_delay in this situation?

I've two FPGAs working on board. The first fpga has a output data port connected to the 2nd fpga to transmit data. And the sampling clock to sample the data in the 2nd fpga also came from the first fpga.

And this clock is generated from a pll output clk and inverted by

"assign output_clk=~pll_clk" in the first fpga(will it be a problem to generate the inverted clock like this rather than using a pll to do the inversion?)

So how to generate the virtual clock for constraining the output delay?

In this case, I think I should just use create_generated_clock to generate the actual output clock and use that clock in the set_output_delay, right?

So it wil be:

create_generated_clock -name fpga2_clk_ext -source [get_pins {PLLFORDDRCLK|altpll_component|auto_generated|pll1|clk[1]}] -divide_by 1 -multiply_by 1 -invert [get_ports {fpga2_sampling_clk}]

set_output_delay fpga2_clk_ext -max...

set_output_delay fpga2_clk_ext -min...

Thanks a lot for giving any suggestions.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Since you are using a source synchronous interface between two FPGAs, rather than inverting the clock on the transmit side, why not just use the opposite edge of the clock to capture the data on the receive side? (I'm assuming this is an SDR interface, and not DDR).

    That being said, let's discuss the current scheme of inverting the transmit clock. If you still want to do this, the best way is to use the ALTDDIO_OUT MegaFunction to invert the clock. Tie the HI input to GND and the LO input to VCC, and this will have the effect of inverting the clock. This will also give you the least amount of skew between your clock and transmit data. (Also, if skew is a concern, I recommend using ALTDDIO_OUT MFs for the data as well instead of regular registers, just connect the HI and LO inputs to the same output data stream).

    The way you are currently doing this, the output clock will be inverted through the output buffer. The time to traverse this buffer will be very different than the clock-to-output delay for your data, and this will create an offset between your clock and your data so that it may not be as close to 180 degrees as you may want (depending on your clock frequency).