How to set_output_delay in this situation?

Since you are using a source synchronous interface between two FPGAs, rather than inverting the clock on the transmit side, why not just use the opposite edge of the clock to capture the data on the receive side? (I'm assuming this is an SDR interface, and not DDR).

That being said, let's discuss the current scheme of inverting the transmit clock. If you still want to do this, the best way is to use the ALTDDIO_OUT MegaFunction to invert the clock. Tie the HI input to GND and the LO input to VCC, and this will have the effect of inverting the clock. This will also give you the least amount of skew between your clock and transmit data. (Also, if skew is a concern, I recommend using ALTDDIO_OUT MFs for the data as well instead of regular registers, just connect the HI and LO inputs to the same output data stream).

The way you are currently doing this, the output clock will be inverted through the output buffer. The time to traverse this buffer will be very different than the clock-to-output delay for your data, and this will create an offset between your clock and your data so that it may not be as close to 180 degrees as you may want (depending on your clock frequency).