How to say for compiler that this note has 50MHz in schematic ?

You dont. You let the compiler compile your code. And then you supply timing specs to see if your code is capable of running at the specified clock frequency. If there are any issues then you can modify the code to improve timing by reducing the logic between registers etc.

For simulation, are you talking about simulating a post-compilation netlist? With good design practice (everything synchronous), good RTL simulation and the correct timing specs (in SDC file) you should be able to miss out the slow timing simulations and test directly on hardware.