KJian6
New Contributor
7 years agoHow to remove the Unused_RX_Clock_Workaround_PMR_CDR_PLL which inserted by Quartus Prime fitter ?
Hi,
I have a FPGA system which include both DDR4 IP and USB3 controller. The Quartus prime 18.1 build 222 has inserted lots of Unused_RX_Clock_Workaround_PMR_CDR_PLL during place&route:
UNUSED_RX_CLOCK_WORKAROUND_FITTER_INSERTED_PMA_CDR_PLL0 :
Location : HSSIPMACDRPLL_1C0
datarate ; 1.0 ms
output_clock_frequency ; 2.9 ms
reference_clock_frequency ; 100us
vco_freq ; 8.0ms
...............
How to get rid of these UNUSED_WORKAROUND PLLs?
Thanks!