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KJian6's avatar
KJian6
Icon for New Contributor rankNew Contributor
7 years ago

How to remove the Unused_RX_Clock_Workaround_PMR_CDR_PLL which inserted by Quartus Prime fitter ?

Hi, I have a FPGA system which include both DDR4 IP and USB3 controller. The Quartus prime 18.1 build 222 has inserted lots of Unused_RX_Clock_Workaround_PMR_CDR_PLL during place&route: U...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Dear KJian6,

I have tried the command in my DDR4 example design and its work. The Fitter successfully generated without any “Transmitter PLLs”. I attached together my .QAR example design for your reference.

You can see in my .QSF (line 190 and 191) which I turn OFF the “ENABLE_UNUSED_RX_CLOCK_WORKAROUND”. Please also note that you need to add both of the command in your .QSF before compilation. For the <pin name>, its actually depend on your design. I recommend you to try the pin that fit into your design.

Hope this helps.

Thanks

Regards

NAli1