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Altera_Forum
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10 years ago

How to recombine LVDS data received from ADC in FPGA.

I am configuring an Analog to Digital Converter(ADC) reciently. I use AD9265. It works in LVDS mode, not CMOS mode. I learn something about LVDS from the datasheet of AD9265. It's my first time to learn LVDS.

In LVDS output mode, data is output as double data rate with the even numbered output bits transitioning near the rising edge of DCO and the odd numbered output bits transitioning near the falling edge of DCO. This is from the datasheet. And I will attach a data output timing graph of AD9265.

But I don't konw how to recombine the data received from AD9265 in FPGA.

Is there anyone who can help me? It troubles me a lot.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    LVDS is a common io standard that FPGA's support. The signals are in P/N pairs (Positive/Negative), The IO Buffers can be set to receive or drive LVDS, but the pair of pins required is fixed, Look at the IO pins available and see if you can find the specific P/N designations.

    Once that is done internally you use the pins just like normal. It looks the the clock in this case is just a 1 to 1 with the data, so it should be pretty easy. For higher speed LVDS signals, (like video), the clock runs at a fraction of the data rate like 1/7 or 1/8, so you need a PLL to clock in the data, so it gets a bit more complex to align the data, but there are Megawizard functions that help with this.

    Pete

    d
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The AD_9625 on my board works in external pin mode. And the output is LVDS mode. Output data format is selected for two complement.

    Just as datasheet od AD_9625 says, 8-bit even numbered output bits(D14_D12_D10_D8_D6_D4_D2_D0) transit near the rising edge of DCO and 8-bit odd numbered output bits(D15_D13_D11_D9_D7_D5_D3_D1).Then I recombine a 16-bit output data(D15_D14_D13_D12_D11_D10_D9_D8_D7_D6_D5_D4_D3_D2_D1_D0) in a DCO clock.

    The AD_9625 works without analog input so it tracks noise in air. Then I observe the results in Signal Tap in FPGA. The 16-bit output data is 1011,1111,11xx,xxxx.It is in two complment. It means that it is a very small negative data.But the amplitude of noise in air should be very small and both in positive and negative.

    The MSB of 8-bit odd numbered output bits(D15_D13_D11_D9_D7_D5_D3_D1) always is 1.what's more,the MSB of 8-bit even numbered output bits(D14_D12_D10_D8_D6_D4_D2_D0) always is 0.

    I don't know where I misunderstand. Can you help me ?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    BFxx is a fairly large negative number. you are measuring in Air, so you could have a significant DC offset on your input.

    Have you tried just driving the AD9625 with a sin wave and see what you get? Does the resulting data look like a sin wave?

    If so, can you actually drive it to a significant value, before it saturates your front end, or does the front end saturate in one direction before the other.

    Without the whole circuit, it's hard to say where the issue is originating form, but it looks like you are combining the data properly. So my expectation is there some DC offset happening on the analog side.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Before going for the full design I would simulate your FPGA code with a serialised ramp as an input and make sure you can decode it correctly. Then you can bring in the ADC.

    Once you have got your simulation working, you can connect up the SPI of the ADC and write into register 0x0D. This according to the datasheet should make the ADC output one of the different test modes. Once you are decoding the test patterns correctly you know your circuit and FPGA code are working together.