Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHow to recombine LVDS data received from ADC in FPGA.
I am configuring an Analog to Digital Converter(ADC) reciently. I use AD9265. It works in LVDS mode, not CMOS mode. I learn something about LVDS from the datasheet of AD9265. It's my first time to ...
Altera_ForumHonored Contributor
Honored ContributorThe AD_9625 on my board works in external pin mode. And the output is LVDS mode. Output data format is selected for two complement.
Just as datasheet od AD_9625 says, 8-bit even numbered output bits(D14_D12_D10_D8_D6_D4_D2_D0) transit near the rising edge of DCO and 8-bit odd numbered output bits(D15_D13_D11_D9_D7_D5_D3_D1).Then I recombine a 16-bit output data(D15_D14_D13_D12_D11_D10_D9_D8_D7_D6_D5_D4_D3_D2_D1_D0) in a DCO clock. The AD_9625 works without analog input so it tracks noise in air. Then I observe the results in Signal Tap in FPGA. The 16-bit output data is 1011,1111,11xx,xxxx.It is in two complment. It means that it is a very small negative data.But the amplitude of noise in air should be very small and both in positive and negative. The MSB of 8-bit odd numbered output bits(D15_D13_D11_D9_D7_D5_D3_D1) always is 1.what's more,the MSB of 8-bit even numbered output bits(D14_D12_D10_D8_D6_D4_D2_D0) always is 0. I don't know where I misunderstand. Can you help me ?
