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Honored Contributor
Honored ContributorHow to recombine LVDS data received from ADC in FPGA.
I am configuring an Analog to Digital Converter(ADC) reciently. I use AD9265. It works in LVDS mode, not CMOS mode. I learn something about LVDS from the datasheet of AD9265. It's my first time to ...
Altera_ForumHonored Contributor
Honored ContributorLVDS is a common io standard that FPGA's support. The signals are in P/N pairs (Positive/Negative), The IO Buffers can be set to receive or drive LVDS, but the pair of pins required is fixed, Look at the IO pins available and see if you can find the specific P/N designations.
Once that is done internally you use the pins just like normal. It looks the the clock in this case is just a 1 to 1 with the data, so it should be pretty easy. For higher speed LVDS signals, (like video), the clock runs at a fraction of the data rate like 1/7 or 1/8, so you need a PLL to clock in the data, so it gets a bit more complex to align the data, but there are Megawizard functions that help with this. Pete d
