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Altera_Forum
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15 years ago

How to properly constrain data/strobe output?

Hi,

I have an FPGA driving an external register with data and clock signals. Both the data and the clock is generated through state machines in the FPGA (see attached simplified picture). I am trying to properly setup the TimeQuest constraints so that the setup and hold times of the exernal register is part part of the timing analysis.

My understanding is that one should create a generated clock for the Stb output and then use set_output_delay -max and -min to cosntrain setup and hold times. I have run into difficulty creating the ganrated clock.

I have tried the following:

create_generated_clock -name Stb_clk -source Sys_Clk -divide_by 1 [get_ports {Stb}]

When I update the timing netlist I get the following warnings / errors:

Warning: Node: ...|HPIController:hpictrl|snHDS1 was determined to be a clock but was found without an associated clock assignment.

Warning: No paths exist between clock target "pHPI_nHDS1" of clock "HpiStb_clk" and its clock source. Assuming zero source clock latency.

(Note I have left the original names in the errors: snHDS1 is the name of the output of FF_Stb. It gets directly assigned - i.e no logic inbetween - to pHPI_nHDS1, which is the name of the port). The problem is that TimeQuest does not account fo the skew between the Sys_Clk and the Stb output pin.

What I then did was to say:

create_generated_clock -name Stb_clk_tmp -source Sys_Clk -divide_by 1 [get_pins {FF_Stb|q}]

create_generated_clock -name Stb_clk -source Stb_clk_tmp -divide_by 1 [get_ports {Stb}]

This seems to work and on first sight the setup / hold analysis seems right. But it does not feel right to create two clocks. Is there another way to do this? Am I doing something wrong?

Regards,

Niki

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    The thumbprint shows that bot the output Clock and Data are generated by a common (internal) clock. This is typical for SPI -like circuits. The output clock is at maximum 1/2 the input clock. If you assure that the output data changes with the clock output going low, you have a setup and hold time to the external device of 1 internal clock cycle. The only thing necessary is to constrain the Tco of the output clock and data in regard with the internal clock using set_output_delay (-max and -min). If the generated output clock is reasonably low, say 10 MHz or so, you can get away by declaring a false path for the outputs.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    You may want to check http://www.altera.com/support/examples/timequest/exm-tq-basic-source-sync.html (http://www.altera.com/support/examples/timequest/exm-tq-basic-source-sync.html). In your case, replace the PLL name with your clock register name.

    --- Quote Start ---

    Hi,

    I have tried the following:

    create_generated_clock -name Stb_clk -source Sys_Clk -divide_by 1 [get_ports {Stb}]

    When I update the timing netlist I get the following warnings / errors:

    Warning: Node: ...|HPIController:hpictrl|snHDS1 was determined to be a clock but was found without an associated clock assignment.

    Warning: No paths exist between clock target "pHPI_nHDS1" of clock "HpiStb_clk" and its clock source. Assuming zero source clock latency.

    (Note I have left the original names in the errors: snHDS1 is the name of the output of FF_Stb. It gets directly assigned - i.e no logic inbetween - to pHPI_nHDS1, which is the name of the port). The problem is that TimeQuest does not account fo the skew between the Sys_Clk and the Stb output pin.

    What I then did was to say:

    create_generated_clock -name Stb_clk_tmp -source Sys_Clk -divide_by 1 [get_pins {FF_Stb|q}]

    create_generated_clock -name Stb_clk -source Stb_clk_tmp -divide_by 1 [get_ports {Stb}]

    This seems to work and on first sight the setup / hold analysis seems right. But it does not feel right to create two clocks. Is there another way to do this? Am I doing something wrong?

    Regards,

    Niki

    --- Quote End ---

    You don't need the clock on the output port, if you use the -reference_pin. Something like:

    create_generated_clock -name Stb_clk_tmp -source Sys_Clk -divide_by 1 [get_pins {FF_Stb|q}]

    set_output_delay -clock Stb_clk_tmp -reference_pin [get_ports Stb] 1.200 [get_ports data_out]

    Hope this helps

    DK
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    You don't need the clock on the output port, if you use the -reference_pin. Something like:

    create_generated_clock -name Stb_clk_tmp -source Sys_Clk -divide_by 1 [get_pins {FF_Stb|q}]

    set_output_delay -clock Stb_clk_tmp -reference_pin [get_ports Stb] 1.200 [get_ports data_out]

    --- Quote End ---

    The '-divide_by 1' is not appropriate as the Stb output clock has a minimum divide of 2 in regard with SysClk as it the output of a FF clocked by Sys_Clk.