How to properly constrain data/strobe output?

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You don't need the clock on the output port, if you use the -reference_pin. Something like:

create_generated_clock -name Stb_clk_tmp -source Sys_Clk -divide_by 1 [get_pins {FF_Stb|q}]

set_output_delay -clock Stb_clk_tmp -reference_pin [get_ports Stb] 1.200 [get_ports data_out]

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The '-divide_by 1' is not appropriate as the Stb output clock has a minimum divide of 2 in regard with SysClk as it the output of a FF clocked by Sys_Clk.