How to properly constrain data/strobe output?

The thumbprint shows that bot the output Clock and Data are generated by a common (internal) clock. This is typical for SPI -like circuits. The output clock is at maximum 1/2 the input clock. If you assure that the output data changes with the clock output going low, you have a setup and hold time to the external device of 1 internal clock cycle. The only thing necessary is to constrain the Tco of the output clock and data in regard with the internal clock using set_output_delay (-max and -min). If the generated output clock is reasonably low, say 10 MHz or so, you can get away by declaring a false path for the outputs.