How to prevent from automaticaly using DSP block ?

Hello !

I am using VHDL to describe a processor.

I have an entity implementing a multiplication.

When synthesizing, DSP blocks are used. I need to run tests on implementations where logic is used instead of DSP blocks (still on the same board, Stratix III epsl150)

How can I do ?

I did not find any option about not inferring DSP blocks in the Synthesis Settings.

I hope you be able to help me.

Thank you in advance