How to package a custom IP containing IP as submodule

Hi,

I have created simple design where I instantiate LPM_sub_add IP as submodule. I would like to package the whole top level so that I can reuse IP. Below are the steps used:

1. Create a new component in Platform designer.
2. I added the .qip file of the IP along with top VHDL file in the synthesis files.

While generating the complete IP I am seeing bunch of errors:

Error: Component add1 can't instantiate a custom component with the same name as itself

Error: add1.add1_0.add1_0: Component add1 1.0 not found or could not be instantiated

Error: add1.clk_0.clk/add1_0.clock: Missing connection end (try "Remove Dangling Connections")

Error: add1.add1_0: add1_0.clk must be connected to a clock output

Error: add1.add1_0.add1_0: Component add1 1.0 not found or could not be instantiated

Error: add1.clk_0.clk/add1_0.clock: Missing connection end (try "Remove Dangling Connections")

Error: add1.add1_0: add1_0.clk must be connected to a clock output

Error: add1_0: missing_module does not support generation.

Error: qsys-generate failed with exit code 1: 4 Errors, 3 Warnings

I guess somehow I have to stitch the netlsit but not sure though. I am not sure if I am missing something basic here. Can someone please guide me with the exact steps to package a custom IP which has submodule IPs?

Thanks,