How to Modify Intel EMIF IP for STT-MRAM Support Similar to Xilinx MIG Patch Mechanism?

Hi Cleveland,

Technically we EMIF IP for Agilex 7 F/I series can support DDR4 and QDRIV only.

The MRAM support is not available.

As you have go through the EMIF User Guide, your analysis and observation is correct as the EMIF IP doesn't has the options per your description.

"Is it possible to patch or deeply customize Intel's EMIF IP core in a way similar to patching Xilinx's MIG RTL, to fully support the special requirements of STT-MRAM?"

• I think it is not possible since it might need to have a different set of calibration method to calibrate this type of memory.

"If not, are there recommended workflows for issuing custom mode register writes (e.g., dynamic MR0[13] switching), scram flows, or for controlling initialization and fail-safe operations with user logic?"

• We don't have recommendation for this workflows.

"Is there any roadmap for making the EMIF IP more open/extensible for persistent memory (MRAM) applications in the future?"

• Unfortunately, we don't have that too.

Regards,

Adzim