How to Modify Intel EMIF IP for STT-MRAM Support Similar to Xilinx MIG Patch Mechanism?

Hi all,

I am currently working on a project that aims to use STT-MRAM (specifically, devices that are compatible at the DDR4 interface level but require special initialization and timing control) with Intel Agilex FPGAs. In the Xilinx FPGA ecosystem, this is typically achieved by generating a standard DDR4 MIG (Memory Interface Generator) core and then applying a patch script provided by the MRAM vendor (such as Everspin) to modify timing parameters, page size, queue depth, initialization sequence (such as NOMEM mode and anti-scribble logic), and power-fail/scram protection logic in the RTL.

I have read the Intel® Agilex™ FPGA EMIF IP User Guide and experimented with the Parameter Editor. It appears that most timing parameters and basic DDR4 configurations can be set during parameterization, but I did not find options for:

• Fully customizing the initialization and mode register write sequence (e.g., special handling of MR0[13] for anti-scribble)

• Adding user-defined signals and queues to implement scram or power-fail logic

• Modifying page size, FIFO depth, or command queue length beyond standard limits

• Overriding the address mapping scheme (ROW-BANK-COL order) to optimize wear and bus utilization for persistent memory

My main questions are:

1. Is it possible to patch or deeply customize Intel's EMIF IP core in a way similar to patching Xilinx's MIG RTL, to fully support the special requirements of STT-MRAM?

2. If not, are there recommended workflows for issuing custom mode register writes (e.g., dynamic MR0[13] switching), scram flows, or for controlling initialization and fail-safe operations with user logic?

3. Is there any roadmap for making the EMIF IP more open/extensible for persistent memory (MRAM) applications in the future?

Any official guidance, user experience, or technical workarounds would be greatly appreciated. Thank you!