Occasional ContributorHi,
I have two clock sources, both with 100Mhz. How to make sure that the clock are in phase?
Data from register A with clock A to register B with clock B.
Do I need to set any SDC or Quartus tool will take care of it?
Thanks
Best way is to source both clocks from the same PLL. You don't say where these clocks are coming from. Feed one into a PLL and then create two mirrored outputs.
Super ContributorBest way is to source both clocks from the same PLL. You don't say where these clocks are coming from. Feed one into a PLL and then create two mirrored outputs.
Occasional ContributorIf they they cannot be feed into one PLL , is it possible to align two clock source with same frequency ?
I have another question, I have one pair coreclkout with 125Mhz and one input clock source with 100Mhz , how do I constrain the sdc, the latch clk 100Mhz could latch the data a few cycle later.
Super Contributorcreate_clock constraint on the 100 MHz input, created_generated_clock on the 125MHz clock. I'm not sure what you mean about latching data a few cycles later. That isn't part of defining the timing constraints for clocks.
Regular ContributorHi,
Does the above comment help?
Regards,
Nurina
Occasional ContributorThe clka and clkb cannot be generated from the PLL. Is it possible to align through sdc constraint so that they are in phase?
Regular ContributorHi,
Are these clocks coming from 2 different sources outside the FPGA?
You could use set_clock_latency if you know what is the additional delay: https://www.intel.com/content/www/us/en/docs/programmable/683243/21-3/set-clock-latency-set-clock-latency.html
If the clocks are sourced from the FPGA, I don't think you can use sdc constraints, you would need them to come from the same source. As mentioned in the above comment, best way is to source both clocks with a PLL.
Regards,
Nurina
Regular ContributorHi,
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Regards,
Nurina
