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Chris039's avatar
Chris039
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

How to make sure clocks are in phase?

Hi, I have two clock sources, both with 100Mhz. How to make sure that the clock are in phase? Data from register A with clock A to register B with clock B. Do I need to set any SDC or Quart...
  • sstrell's avatar
    sstrell
    3 years ago

    Best way is to source both clocks from the same PLL. You don't say where these clocks are coming from. Feed one into a PLL and then create two mirrored outputs.

Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Are these clocks coming from 2 different sources outside the FPGA?

You could use set_clock_latency if you know what is the additional delay: https://www.intel.com/content/www/us/en/docs/programmable/683243/21-3/set-clock-latency-set-clock-latency.html


If the clocks are sourced from the FPGA, I don't think you can use sdc constraints, you would need them to come from the same source. As mentioned in the above comment, best way is to source both clocks with a PLL.


Regards,

Nurina