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Altera_Forum's avatar
Altera_Forum
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9 years ago

How to make all Verilog files being recognized as SystemVerilog files?

Hi All,

How to make all Verilog files in the Quartus-II Project being recognized as SystemVerilog files?

Could it be done in the Project Settings? Where? Is there some special TCL command?

Thank you!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Under 'Project' -> 'Add/Remove files in project', select each file in turn, click 'Properties' and change the 'Type'.

    Alternatively, change all your file extensions to .sv and Quartus will automatically assume they're System Verilog.

    Cheers,

    Alex