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Altera_Forum
Honored Contributor
Honored ContributorHow to make all Verilog files being recognized as SystemVerilog files?
Hi All, How to make all Verilog files in the Quartus-II Project being recognized as SystemVerilog files? Could it be done in the Project Settings? Where? Is there some special TCL command...
Altera_ForumHonored Contributor
Honored ContributorUnder 'Project' -> 'Add/Remove files in project', select each file in turn, click 'Properties' and change the 'Type'.
Alternatively, change all your file extensions to .sv and Quartus will automatically assume they're System Verilog. Cheers, Alex
