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MinzhiWang's avatar
MinzhiWang
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

How to interface between user logic and Qsys(Platform) in AVMM PCIe ref-design?

Hello Guys, I'm studying Avalon-MM DMA PCIe referent design. Our target device is 10cx220yf780e5g. I can find the ref-design from Intel website and correspoinding an doc, an690. But the ref-design...
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MinzhiWang's avatar
MinzhiWang
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi FvM,

Thanks for you reply.

I noticed that the on-chip RAM is connected to several master. Now one more master implemented with me will be connected to it. So how to avoid the confilict among multiple masters to access single on-chip RAM? And how user logic to know when the on-chip RAM is ready for it to access this on-chip ram?

Thanks

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi Minzhi,

You can try to check the Arbitration settings, click on the interconnect that connect the master to ram
properties pane, you can configure the arbitration scheme (e.g., round-robin, priority-based).
Detail, you may refer to 4.7. Avalon® -ST Round Robin Scheduler

The Avalon® -ST Round Robin Scheduler core controls the read operations from a multi-channel Avalon® -ST component that buffers data by channels. The Request Interface is an Avalon® -MM write master interface that requests data from a specific channel. The Avalon® -ST Round Robin Scheduler cycles through the channels it supports and schedules data to be read.

Hope that can help you to move forward.

Regards,

Wincent