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MinzhiWang's avatar
MinzhiWang
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

How to interface between user logic and Qsys(Platform) in AVMM PCIe ref-design?

Hello Guys, I'm studying Avalon-MM DMA PCIe referent design. Our target device is 10cx220yf780e5g. I can find the ref-design from Intel website and correspoinding an doc, an690. But the ref-design...
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,
you can start with the example project and modify the module that connects on-chip RAM as AVMM slave, e.g. xxx_integrated_onchip_memory. You'll use one port for the AVMM and one for the user logic interface. clk, address data and control signals of the user interface have to be exported as conduit which make them appear on the top level of the Qsys design.

MinzhiWang's avatar
MinzhiWang
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi FvM,

Thanks for you reply.

I noticed that the on-chip RAM is connected to several master. Now one more master implemented with me will be connected to it. So how to avoid the confilict among multiple masters to access single on-chip RAM? And how user logic to know when the on-chip RAM is ready for it to access this on-chip ram?

Thanks