How to interface between user logic and Qsys(Platform) in AVMM PCIe ref-design?

Hi,
you can start with the example project and modify the module that connects on-chip RAM as AVMM slave, e.g. xxx_integrated_onchip_memory. You'll use one port for the AVMM and one for the user logic interface. clk, address data and control signals of the user interface have to be exported as conduit which make them appear on the top level of the Qsys design.