Occasional Contributor
Super ContributorHi,
you can start with the example project and modify the module that connects on-chip RAM as AVMM slave, e.g. xxx_integrated_onchip_memory. You'll use one port for the AVMM and one for the user logic interface. clk, address data and control signals of the user interface have to be exported as conduit which make them appear on the top level of the Qsys design.
Occasional ContributorHi FvM,
Thanks for you reply.
I noticed that the on-chip RAM is connected to several master. Now one more master implemented with me will be connected to it. So how to avoid the confilict among multiple masters to access single on-chip RAM? And how user logic to know when the on-chip RAM is ready for it to access this on-chip ram?
Thanks
Regular ContributorHi Minzhi,
You can try to check the Arbitration settings, click on the interconnect that connect the master to ram
properties pane, you can configure the arbitration scheme (e.g., round-robin, priority-based).
Detail, you may refer to 4.7. Avalon® -ST Round Robin Scheduler
The Avalon® -ST Round Robin Scheduler core controls the read operations from a multi-channel Avalon® -ST component that buffers data by channels. The Request Interface is an Avalon® -MM write master interface that requests data from a specific channel. The Avalon® -ST Round Robin Scheduler cycles through the channels it supports and schedules data to be read.
Hope that can help you to move forward.
Regards,
Wincent
