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MinzhiWang's avatar
MinzhiWang
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

How to interface between user logic and Qsys(Platform) in AVMM PCIe ref-design?

Hello Guys, I'm studying Avalon-MM DMA PCIe referent design. Our target device is 10cx220yf780e5g. I can find the ref-design from Intel website and correspoinding an doc, an690. But the ref-design...
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Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi ,


Thanks for reaching, I never implement the same as you.

But I can lay down some of suggestion based on my experience, how that give you some idea to move forward.


  1. Ensure that your custom logic has Avalon-MM interfaces that can communicate with other components in the Qsys system.
  2. Typically, you will need to define Avalon-MM master or slave interfaces depending on whether your logic will be reading from or writing to the on-chip memory.
  3. Add your custom logic as a new component. You can do this by creating a new component in Platform Designer and specifying the Avalon-MM interfaces.
  4. Connect the Avalon-MM interfaces of your custom logic to the appropriate interfaces in the Qsys system. For example, if your custom logic needs to access on-chip memory, connect it to the memory-mapped slave interface of the on-chip memory.


Hope that able to help you to move forward. But we do advise to follow the example design as it is well tested.


Regards,

Wincent



MinzhiWang's avatar
MinzhiWang
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi Wincent,

Thanks for you reply.

In our application, the data are stored in an FIFO. So the data transfer between user logic and Qsys lay on between FIFO and the On-chip memory in Qsys.

As you said, we can't connect FIFO interface to that On-chip memory directly. We have to design one extra AVMM master for our FIFO?

Could you provide some simple tutorial papers for us to learn?

Thanks