I have a design which does single precision computations using Altera Floating point IPs. However since these IPs don't seem to have a 'valid' or 'done' output bit, I'm not able to see how to connect one module to another one. My concern is that how will a successive module know when to take the output from the previous module. Could someone help with this?

A valid or done bit is only meaningful for sequentially operating units. The said FP MegaFunctions are fully pipelined, emitting a new result every clock cycle. The input data must be valid only for one clock cycle, you have to know the pipeline delay, however.

its quite easy just to store a valid bit in parrallel to the floating point units if you need it for other modules.

It would have been smart thinking from the Altera guys if they had provisioned the 'valid' pipeline inside the building block. It would make for a much cleaner design as we don't have to add the glue logic mentioned by Tricky. While we at it: can we have a separate clock enable for every stage too? I have a dataflow based development environment, but because all of Altera's building blocks use a global clock enable I'll be stuck when I would need more advanced functionality (or with a pipeline greater than 1).

Could anyone give a small code example to show what the glue logic about the parallel bit is being talked about?

The "parallel" valid bit chain is simply a shift register (respectively a number of cascaded D-FFs), the delay (number of stages) is equal to the pipeline delay of the respective IP block. I aggree, that Altera could have added it as an option, but as mentioned above, it won't be of any use in the standard application, where a continous data stream is fed to the IP.

How to interconnect modules without 'valid' or 'done' output signal

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Altera_Forum
Honored Contributor
15 years ago
My bad, I had overlooked the delays introduced by me in my testbench which were reflected in my output. Now that I'm giving input in every clock cycle after the first delay of 17 clock cycles, one output appears every new clock cycle.
Altera_Forum
Honored Contributor
15 years ago
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I aggree, that Altera could have added it as an option, but as mentioned above, it won't be of any use in the standard application, where a continous data stream is fed to the IP.
--- Quote End ---

Even a continuous data stream has a beginning (and in what most of us call a continuous video stream there are regular gaps) so an 'embedded' valid bit will almost always come in handy, and in case you really don't need it the complier would optimize it away.

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How to interconnect modules without 'valid' or 'done' output signal

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