How to interconnect modules without 'valid' or 'done' output signal

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I aggree, that Altera could have added it as an option, but as mentioned above, it won't be of any use in the standard application, where a continous data stream is fed to the IP.

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Even a continuous data stream has a beginning (and in what most of us call a continuous video stream there are regular gaps) so an 'embedded' valid bit will almost always come in handy, and in case you really don't need it the complier would optimize it away.