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Altera_Forum's avatar
Altera_Forum
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15 years ago

How to interconnect modules without 'valid' or 'done' output signal

I have a design which does single precision computations using Altera Floating point IPs. However since these IPs don't seem to have a 'valid' or 'done' output bit, I'm not able to see how to connect one module to another one. My concern is that how will a successive module know when to take the output from the previous module. Could someone help with this?

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    My bad, I had overlooked the delays introduced by me in my testbench which were reflected in my output. Now that I'm giving input in every clock cycle after the first delay of 17 clock cycles, one output appears every new clock cycle.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    I aggree, that Altera could have added it as an option, but as mentioned above, it won't be of any use in the standard application, where a continous data stream is fed to the IP.

    --- Quote End ---

    Even a continuous data stream has a beginning (and in what most of us call a continuous video stream there are regular gaps) so an 'embedded' valid bit will almost always come in handy, and in case you really don't need it the complier would optimize it away.