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AGaru1's avatar
AGaru1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

How to implement DP RAM written in RTL using M20K?

Hi all, can you please help me to synthetize a ram module written in vhdl as M20K? Unfortunately Quartus is synthetizing it using flipflops so it ends up in a big waste of them. Is there any particu...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

Yes, what you can do is right click on the vhdl/verilog files, insert template.

From there, you can find the method to rewrite the code for your ram and there is also attribute that you can use to infer M20k