New Contributor
Regular ContributorHi,
I have emailed you a ZIP of the Q17.0 CV FFT IP generated design. You may do the following to simulate it:
You should be able to see the example simulation waveform. Please let me know if there is any concern. Thank you.
New ContributorHi, thank you so much for your help.
I did it and it works.
But what I really want is to create a testbench for several blocks in the same schematic, specifically a filter that I will connect to the input of the fft ip.
I actually get the error when performing the rtl simulation after generating the testbench for the fft.
This is what I do:
1.Generate -> generate testbench system
2. start analysis and elaboration
3. RTL simulation
4. Error in modelsim v3033:
** Error: (vsim-3033) c: /intelfpga/17.1/quartus/bin64/db/ip/blockt/submodules/blocktff_fft_ii_0.sv (59): Instantiation of 'asj_fft_si_se_so_bb' failed. The design unit was not found.
...
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./fft_on_top_run_msim_rtl_vhdl.do PAUSED at line 17
It is the first time that I work with this program and it is possible that I am doing something wrong, but I found another person with the same problem and he solved it but with the Pro version. I cannot do the same because I am using the standard version.
https://forums.intel.com/s/question/0D50P00003yyO6LSAU/fft-ip-core-and-modelsim
Thank you for your time,
Ignacio
