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John-Philip's avatar
John-Philip
Icon for New Contributor rankNew Contributor
11 months ago
Solved

How to ignore error 18496 (Output ??? too close to PLL clock input)

Related to: Error (18496): The Output SCLK in pin 26 is too close to PLL clock input in pin 27 Fitter Pin Placement Constraint MAX10 pin too close to PLL clock Pin location is too close to PL...
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RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
11 months ago

I am glad that the issue has been resolved.


FYI, this is the KDB mentioned.

https://www.intel.com/content/www/us/en/support/programmable/articles/000074027.html


I checked the database, and it appears that this patch was restricted to specific customers with a specific Quartus version at that time and was not typically included in future releases.

This likely explains why you are still seeing the issue in later Quartus releases, and an INI file was created to address the problem.


Since a KDB article has been created and a workaround (using the INI) is available, it is unlikely that this issue will be fixed in future Quartus Standard releases.


Please use the INI file to resolve the issue.


Regards,

Richard Tan