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John-Philip's avatar
John-Philip
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1 year ago
Solved

How to ignore error 18496 (Output ??? too close to PLL clock input)

Related to: Error (18496): The Output SCLK in pin 26 is too close to PLL clock input in pin 27 Fitter Pin Placement Constraint MAX10 pin too close to PLL clock Pin location is too close to PL...
Hdl
John-Philip's avatar
John-Philip
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1 year ago

Awesome -- it works! Thank you

In case the link goes broken in future, the solution is:

  1. Create a new file with name "quartus.ini" in current quartus project directory.
  2. Add "disable_max10_e144_pll_inclk_io_rule=on".
  3. Save and re-compile quartus project again.
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

So I guess it wasn't fixed!

  • John-Philip's avatar
    John-Philip
    Icon for New Contributor rankNew Contributor
    1 year ago

    I agree with Quartus's policy -- it is a bad idea to have an output pin next to the clock input. I don't think it's a bug -- I think it's a missing feature (i.e. the ability to easily override the check).
    No matter -- I have the ability to override the check, so I'm very happy