Forum Discussion
John-Philip
New Contributor
New ContributorHow to ignore error 18496 (Output ??? too close to PLL clock input)
Related to: Error (18496): The Output SCLK in pin 26 is too close to PLL clock input in pin 27 Fitter Pin Placement Constraint MAX10 pin too close to PLL clock Pin location is too close to PL...
Hi,
I see the fix has been already published
intel.it/content/dam/support/us/en/programmable/kdb/support/knowledge-center/tools/2016/quartus-16.1-0.01cb-readme.txt
John-PhilipNew Contributor
New ContributorI'll hunt around to see if I can find the "quartus.ini option to disable pll inclock rules"...
