Forum Discussion
John-Philip
New Contributor
New ContributorHow to ignore error 18496 (Output ??? too close to PLL clock input)
Related to: Error (18496): The Output SCLK in pin 26 is too close to PLL clock input in pin 27 Fitter Pin Placement Constraint MAX10 pin too close to PLL clock Pin location is too close to PL...
Hi,
I see the fix has been already published
intel.it/content/dam/support/us/en/programmable/kdb/support/knowledge-center/tools/2016/quartus-16.1-0.01cb-readme.txt
FvM
Super Contributor
Super ContributorHi,
I guess thea reason why specific IO constraints have been set up for MAX10_E144 is relative large cross talk of adjacent pins with this package. Thus you should double check if your pin usage is safe before disabling IO rules. Should be o.k. for a static LED signal.
Regards
Frank
John-PhilipNew Contributor
New ContributorYes. I know. I'm happy that it is safe.
How do I tell Quartus to ignore it?
