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John-Philip
New Contributor
New ContributorHow to ignore error 18496 (Output ??? too close to PLL clock input)
Related to: Error (18496): The Output SCLK in pin 26 is too close to PLL clock input in pin 27 Fitter Pin Placement Constraint MAX10 pin too close to PLL clock Pin location is too close to PL...
Hi,
I see the fix has been already published
intel.it/content/dam/support/us/en/programmable/kdb/support/knowledge-center/tools/2016/quartus-16.1-0.01cb-readme.txt
FvM
Super Contributor
Super ContributorHi,
I was assuming so far that IO_MAXIMUM_TOGGLE_RATE always handles the issue. But I learned from your example that it's not the case.
Apparently it's a MAX10_E144 specific problem. Intel/Altera has implemented an undocumented quartus.ini option to disable pll inclock rules for this device.
I don't feel legitimated to post it here, you'll need to ask your FAE unless Intel will publish it.
Best regards
Frank
