How to handle "_ver" suffix to Altera Verilog libraries? Other source files have hardcoded "use library" with names without that "_ver" suffix

If user revert to Verilog, the Verilog flavor of CycloneV will be parsed. The names of the various altera Verilog libraries all get a “_ver” suffix.

The VHDL libraries do *not* have such suffix.

The result is that when some other VHDL entities have hardcoded “use library” statements, they reference libraries that no longer exists (as we chose Verilog).

This yield elaboration errors, as the VHDL code reference libraries that are not present.