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ARach7
New Contributor
New ContributorHow to handle "_ver" suffix to Altera Verilog libraries? Other source files have hardcoded "use library" with names without that "_ver" suffix
If user revert to Verilog, the Verilog flavor of CycloneV will be parsed. The names of the various altera Verilog libraries all get a “_ver” suffix. The VHDL libraries do *not* have such suffi...
JoanneSinY_L_Intel
Occasional Contributor
Occasional ContributorHi Arach,
Please refer to pdf below pg96. It mentions by specifies the device family which you are compiling the library, it will result in the compilation of all libraries required for RTL and gate level sim
https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/manual/tclscriptrefmnl.pdf
Thanks
Joanne
