Altera_Forum
Honored Contributor
13 years agoHow to force internal RAM usage in Quartus
I have a DE2-70 dev kit and would like to set up a couple of internal RAM 2D bit arrays. I will NOT be using SOPC/Qsys but would like to access these in Verilog. I have looked up the correct way to build a 2D array using reg [117:0] array_name [27:0]; for example. When I compile it using Quartus II 11 sp1 I do not get any usage on the memory bits on the chip. Am I missing something?
According to a previous piece of information I found there is a technique to force usage of internal RAM, but I cannot find an actual recipie for doing this. Any assistance would be much appreciated. Thanks, Geof