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SKGR0's avatar
SKGR0
Icon for New Contributor rankNew Contributor
5 years ago

How to fix the timing violation with an IP (altera_mult_add)

The timing violation is present within the multiplier -ve slack => -2.335 From node mult_2_64x8:lsm_mult3_inst|lsm_mult_2_64x8_0002:mult_2_64x8_inst|altera_mult_add:altera_mult_add_component|alte...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

If you set false path to the irrelevant path, you will not see the timing analysis on the path and there should be only one time compilation. Do you still see the timing analysis on the same path after you apply false path?

Thanks.

Best regards,

KhaiY

  • SKGR0's avatar
    SKGR0
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi KhaiY

    Yes ..i do observe that...

    I want to add another point.

    I see that one lpm_divide instance used in the design consumes 6k MLAB

    And though the timing path is irrelevant , the "to node" points to this divider.

    Is there a way i can make the lpm_divide instance (63x63) be forced to implement using M10Ks ?

    Will this help in improving the timing?

    Regards

    SKGR0