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SKGR0's avatar
SKGR0
Icon for New Contributor rankNew Contributor
5 years ago

How to fix the timing violation with an IP (altera_mult_add)

The timing violation is present within the multiplier -ve slack => -2.335 From node mult_2_64x8:lsm_mult3_inst|lsm_mult_2_64x8_0002:mult_2_64x8_inst|altera_mult_add:altera_mult_add_component|alte...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi SKGR0,

If there is no timing relationship between the two module or irrelevant path, is it possible to false path ?

Thanks.

Best regards,

KhaiY

SKGR0's avatar
SKGR0
Icon for New Contributor rankNew Contributor
5 years ago

Hi

Set as False path

I have tried this .

The process is tedious as the SDC has to be updated and the compilation has to be repeated for more number of iterations (time consuming) to achieve frequency.

Is there an alternate way?

Regards

SKGR0