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SKGR0's avatar
SKGR0
Icon for New Contributor rankNew Contributor
5 years ago

How to fix the timing violation with an IP (altera_mult_add)

The timing violation is present within the multiplier -ve slack => -2.335 From node mult_2_64x8:lsm_mult3_inst|lsm_mult_2_64x8_0002:mult_2_64x8_inst|altera_mult_add:altera_mult_add_component|alte...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Sahana,

We do not receive any response from you to the previous question/reply/answer that I have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Thanks.

Best regards,

KhaiY

  • SKGR0's avatar
    SKGR0
    Icon for New Contributor rankNew Contributor
    5 years ago

    Sorry for the delay

    The problem is design file cannot be shared.

    I would like to receive inputs on how to solve timing issues on irrelevant paths in the system.

    I figured out that the problem was not present in the path that is traceable in the design.

    System is something like this

    a-> b-> c ->d

    where a,b,c,d are modules which work in sequence

    The timing issue is in

    from node : module d

    to node : module b

    (there is not link between these modules in the design)

    Regards

    SKGR0