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Altera_Forum's avatar
Altera_Forum
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8 years ago

How to ensure proper simulation in ModelSim

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY satUpCount ISPORT(clock, en : IN STD_LOGIC; flag8 : OUT STD_LOGIC); END satUpCount; ARCHITECTURE RTL OF satUpCount IS SI...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I mean just general good practice for VHDL logic, usually presented in any decent tutorial - I think altera provides them via the text editor. But stick to this: 


process(clk, async_rst)   -- no other signals. No async reset needed if you dont need one
begin
  if async_rst = '1' then
    -- async reset here
  elsif rising_edge(clk) then
    -- sync logic here, including enables
  end if;
  -- NOTHING goes here
end process;