Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHow to ensure proper simulation in ModelSim
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY satUpCount ISPORT(clock, en : IN STD_LOGIC;
flag8 : OUT STD_LOGIC);
END satUpCount;
ARCHITECTURE RTL OF satUpCount IS
SI...
Altera_ForumHonored Contributor
Honored ContributorThere are several issues here:
1. You have not really used the proper template for registered logic. 2. Synthesis ignores sensitivity lists, simulation does not. The synthesis is generating flag purely from async logic, whereas in your simulation flag can only change when clock or enable change. To match the two behaviours, you either need to add sCntVal to the sensitivity list (or if you use VHDL 2008 you can use process(all) ) or synchronise all of your code. 3. If you follow standard practice, and proper templates, Modelsim behaviour will always match real hardware.
