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Honored Contributor
Honored ContributorHow to ensure multiplexer priority levels coded in VHDL
Hi, How to ensure a value "CAFE" on the register Reg_In with the RTL code:Reg_In <= X"CAFE" when A = '1' else In_1 when K = '1 else In_2 when L...
Altera_ForumHonored Contributor
Honored ContributorThe error occurs on the board. Simulation is OK.
In SignalTap I saw the change of the high byte of Bus reflected in some of the bits of the Reg_in data input. In the Technology Map view, the implementation of the low byte part of the multiplexer is according the VHDL. The high byte is mapped differently. The input for A is half way the mapped multiplexer structure and not in the last stage of the multiplexer as described in the RTL code. Why is this done this way? How to overcome, force the right RTL implementation?
