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Altera_Forum's avatar
Altera_Forum
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8 years ago

How to ensure multiplexer priority levels coded in VHDL

Hi, How to ensure a value "CAFE" on the register Reg_In with the RTL code:Reg_In <= X"CAFE" when A = '1' else In_1 when K = '1 else In_2 when L...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Quartus will only synthesise what you write.

The snippet you posted says that Reg_in will be x"CAFE" when A = 1. If you are having problems, then I suggest there is a problem in the design somewhere. Where are you seeing the problems? simulation, or on the board?

Without the whole code, there isnt much more I can say.