Altera_Forum
Honored Contributor
15 years agoHow to enable Timing-driven compilation
Hi,
When I compile my project, I got a warning as below, --- Quote Start --- Warning: Timing-driven compilation is disabled - timing performance will not be optimized --- Quote End --- I checked the setting file. I assume settings about timing are set to ON. I wonder do I make some mistake with .qsf file? Regards, Clairlyn Some sections of my .qsf:# Classic Timing Assignments
# ==========================
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name REMOVE_DUPLICATE_LOGIC OFF
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name SAFE_STATE_MACHINE ON
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
# Fitter Assignments
# ==================
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name SEED 3
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE NORMAL
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name ECO_OPTIMIZE_TIMING ON
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON