Altera_ForumHonored Contributor15 years agoHow to enable Timing-driven compilation Hi, When I compile my project, I got a warning as below, --- Quote Start --- Warning: Timing-driven compilation is disabled - timing performance will not be optimized --- Quote End ...Show More
Altera_ForumHonored Contributor15 years agoYou need to compile your sdc in Time Quest Analyzer. Then the synthesis will be sdc driven.
Recent DiscussionsTiming analysis - long combinational pathQuartusPro 25.3 Crashed after using the Signal Tap Logic AnalyzerDuplicate_hierarchy_depth / duplicate_registerAutomatically added negative node for TDS output doesn't work with Agilex 5Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG