How to dynamically adjust PLL phase

I use a 4 MHz reconfig clock. Upon the final reconfig pulse or a loss of lock, I hold the PLL in reset for 512 clocks. I don't just nudge the phase. My application is to change the fundamental clock rate. So, reset makes sense. I seem to recall I originally tried to run closer to the rated speed of the reconfig, but backed off to 4 MHz for timing reasons that were not well documented/reported. Again, this was with an older rev. of Quartus.