Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

How to dynamically adjust PLL phase

Hi, I am using Quartus 7.2 SP1. I am currently trying to implement a reconfigurable PLL for debug purposes. I am using an367 (http://www.altera.com/literature/an/an367.pdf) as a reference. I wa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

The document you're using talks about 3 reference designs at the end, which you should be able to download from the same place you downloaded the AN367 document. The second one should be the one you're looking for.

Beware in reconfiguring though. Making changes to anything other than the post-scale counter or the phase will result in a PLL loss. That's what I'm currently trying to figure out is how to reacquire the lock. Perhaps someone will have an answer for that.