How to disable most synthesis-optimizations options?

Hello Abe,

thank you for your answer and for looking at my project.

I want to implement butterfly PUF Cells as introduced in https://www.researchgate.net/publication/4349783_Extended_abstract_the_butterfly_PUF_protecting_IP_on_every_FPGA

Yes, you're right. I have made a mistake.

1. Clock should be always high

2. PRE of FF 1 and CLR of FF 2 should be always low

But after this changes Quartus removes my Butterfly-Cells and connects the SZx_Out Pins to GND and i still don't know why... Quartus tells me "Warning (13024): Output pins are stuck at VCC or GND"

I have already implemeted Butterfly-Cells on an Xilinx Spartan3e FPGA with Xilinx ISE with the same vhdl Files and it worked just fine.

You can find a version with correct conected Butterfly-Cells below.

Best regards

Johannes